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19-2747; Rev 4; 4/05
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection
General Description
The MAX7311 2-wire-interfaced expander provides 16-bit parallel input/output (I/O) port expansion for SMBusTM and I2CTM applications. The MAX7311 consists of input port registers, output port registers, polarity inversion registers, configuration registers, a bus timeout register, and an I2C-compatible serial interface logic compatible with SMBus. The system master can invert the MAX7311 input data by writing to the active-high polarity inversion register. The system master can enable or disable bus timeout by writing to the bus timeout register. Any of the 16 I/O ports can be configured as an input or output. A power-on reset (POR) initializes the 16 I/Os as inputs. Three address select pins configure one of 64 slave ID addresses. The MAX7311 supports hot insertion. All port pins, the INT output, SDA, SCL and the slave address inputs AD0-2 remain high impedance in power down (V+ = 0V) with up to 6V asserted upon them. The MAX7311 is available in 24-pin SO, SSOP, TSSOP, and thin QFN packages and is specified over the -40C to +125C automotive temperature range. For applications requiring I/Os without pullup resistors, refer to the MAX7312 data sheet. 2V to 5.5V Operation 5V Overvoltage Tolerant I/Os Supports Hot Insertion 16 I/O Pins that Default to Inputs on Power-Up 100k Pullup on Each I/O Open-Drain Interrupt Output (INT) Bus Timeout for Lock-Up-Free Operation Noise Filter on SCL / SDA Inputs 64 Slave ID Addresses Available Low Standby Current (2.9A typ) Polarity Inversion 4mm 4mm, 0.8mm Thin QFN Package -40C to +125C Operation
Features
400kbps I2C-Compatible Serial Interface
MAX7311
Ordering Information
PART TEMP RANGE PIN-PACKAGE PKG CODE -- -- T2444-4 --
Applications
Servers RAID Systems Industrial Control Medical Equipment PLCs Instrumentation and Test Measurement
MAX7311AWG -40C to +125C 24 Wide SO MAX7311AAG MAX7311ATG MAX7311AUG -40C to +125C 24 SSOP -40C to +125C 24 Thin QFN (4mm 4mm)
-40C to +125C 24 TSSOP
SMBus is a trademark of Intel Corp. Purchase of I2C components of Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Phillips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Phillips.
Pin Configurations
I/O15 I/O12 14 24 V+ SCL 19 AD1 2 AD2 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 I/O4 8 I/O5 9 I/O6 10 I/O7 11 GND 12 23 SDA SDA 20 22 SCL V+ 21 21 AD0 10 I/O8 INT 22 20 I/O15 AD1 23 19 I/O14 AD2 24 18 I/O13 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 17 I/O12 16 I/O11 15 I/O10 14 I/O9 13 I/O8 1 2 3 4 5 6 7 I/O6 8 I/O7 11 I/O9 18 17 16 I/O14 15 13 12 I/O10 I/O11 AD0
TOP VIEW
INT 1
MAX7311
MAX7311ATG
I/O13
9
GND
THIN QFN
TSSOP/SSOP/SO
________________________________________________________________ Maxim Integrated Products
1
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2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
ABSOLUTE MAXIMUM RATINGS
V+ to GND ................................................................-0.3V to +6V I/O0-I/O15 as Inputs ....................................(GND - 0.3V) to +6V SCL, SDA, AD0, AD1, AD2, INT...................(GND - 0.3V) to +6V Maximum V+ Current ......................................................+250mA Maximum GND Current ...................................................-250mA DC Input Current on I/O0-I/O15 .......................................20mA DC Output Current on I/O0-I/O15 ....................................80mA Continuous Power Dissipation (TA = +70C) 24-Pin Wide SO (derate 11.8mW/C above +70C) ....941mW 24-Pin SSOP (derate 8.0mW/C above +70C) ...........640mW 24-Pin TSSOP (derate 12.2mW/C above +70C) .......975mW 24-Pin Thin QFN (derate 20.8mW/C above +70C) .1668mW Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25C.) (Note 1)
PARAMETER Supply Voltage Supply Current SYMBOL V+ V = 2V I+ All I/Os unloaded, fSCL = 400kHz All I/Os unloaded, fSCL = 0 V+ = 3.3V V+ = 5.5V V+ = 2V Standby Current Power-On Reset Voltage SCL, SDA Input Voltage Low Input Voltage High Low-Level Output Voltage Leakage Current Input Capacitance I/O_ Input Voltage Low Input Voltage High Input Leakage Current Internal Pullup Current Low-Level Output Current ISINK VIL VIH TA = -40C to +85C; includes internal pullup current, VIO = V+ TA = -40C to +85C, VIO = 0 V+ = 2V, VOL = 0.5V V+ = 3.3V, VOL = 0.5V V+ = 5V, VOL = 0.5V High Output Current AD0, AD1, AD2 Input Voltage Low Input Voltage High VIL VIH 0.7 V
+ +
CONDITIONS
MIN 2
TYP 23 43 80 2.3 2.9 3.8 1.4
MAX 5.5 35 60 120 11 12 15.5 1.7 0.3 V+
UNITS V A
ISTBY VPOR VIL VIH VOL IL
V+ = 3.3V V+ = 5.5V
A V V V V A pF
0.7 V ISINK = 6mA -1
+
0.4 +1 10 0.8 1.8 1 34 8.5 17 29 17 32 43 41 31 0.3 V+ 100
V V A A mA
ISOURCE
V+ = 3.3V, VOH = 2.4V V = 5V, VOH = 4.5V
+
mA
V V
2
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2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2V to 5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25C.) (Note 1)
PARAMETER Leakage Current Input Capacitance INT Low-Level Output Current IOL VOL = 0.4V 6 mA SYMBOL CONDITIONS MIN -1 4 TYP MAX +1 UNITS A pF
MAX7311
AC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA = -40C to +125C, unless otherwise noted.) (Note 1)
PARAMETER SCL Clock Frequency Bus Timeout Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Low Period SCL High Period SDA Fall Time Pulse Width of Spike Suppressed PORT TIMING Output Data Valid Input Data Setup Time Input Data Hold Time INTERRUPT TIMING Interrupt Valid Interrupt Reset tIV tIR Figure 9 Figure 9 30.5 2 s s tPV Figure 7 27 0 3 s s s SYMBOL fSCL tTIMEOUT tBUF tHD,STA tSU,STA tSU,STO tHD,DAT tSU,DAT tLOW tHIGH tF tSP Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 (Note 3) Figure 2 Figure 2 Figure 2 Figure 2 (Notes 4, 5) (Note 6) V+ < 3.3V V+ 3.3V 50 100 1.3 0.7 500 250 (Note 2) 29 1.3 0.6 0.6 0.6 0.9 CONDITIONS MIN TYP MAX 400 61 UNITS kHz ms s s s s s ns s s ns ns
Note 1: All parameters are 100% production tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Minimum SCL clock frequency is limited by the MAX7311 bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation. Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL signal) in order to bridge the undefined region SCL's falling edge. Note 4: CB = total capacitance of one bus line in pF. Note 5: The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tF. Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. _______________________________________________________________________________________ 3
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX7311 toc01
STANDBY SUPPLY CURRENT vs. TEMPERATURE
8 SUPPLY CURRENT (A) 7 6 5 4 3 2 1 0 V+ = 2V V+ = 3.3V SCL = V+ ALL I/Os UNLOADED V+ = 5V
MAX7311 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
90 80 SUPPLY CURRENT (A) 70 60 50 40 30 20 10 0 fSCL = 400kHz ALL I/Os UNLOADED
MAX7311 toc03
100 90 80 SUPPLY CURRENT (A) 70 60 50 40 30 20 10 0 -50
fSCL = 400kHz ALL I/Os UNLOADED V+ = 5V
9
100
V+ = 3.3V
V = 2V
+
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
I/O SINK CURRENT vs. OUTPUT LOW VOLTAGE
MAX7311 toc04
I/O SINK CURRENT vs. OUTPUT LOW VOLTAGE
MAX7311 toc05
I/O SINK CURRENT vs. OUTPUT LOW VOLTAGE
V+ = 5V TA = -40C 45 40 35 TA = +25C
MAX7311 toc06
24 22 20 18 16 ISINK (mA) 14 12 10 8 6 4 2 0 0
V+ = 2V TA = -40C
50 45 40 35 ISINK (mA)
V+ = 3.3V TA = -40C
50
TA = +25C
25 20 15 10 5 0 TA = +125C
ISINK (mA)
TA = +25C
30
30 25 20 15 10 5 0 TA = +125C
TA = +125C
0.1
0.2
0.3 VOL (V)
0.4
0.5
0.6
0
0.1
0.2
0.3 VOL (V)
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
I/O OUTPUT LOW VOLTAGE vs. TEMPERATURE
MAX7311 toc07
I/O SOURCE CURRENT vs. OUTPUT HIGH VOLTAGE
MAX7311 toc08
I/O SOURCE CURRENT vs. OUTPUT HIGH VOLTAGE
V+ = 3.3V TA = -40C 45 40 35 ISOURCE (mA) 30 25 20 15 10 5 TA = +125C TA = +25C
MAX7311 toc09
400 350 300 V+ = 5V, ISINK = 10mA
25
V+ = 2V TA = -40C TA = +25C
50
20 ISOURCE (mA)
VOL (mV)
250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) V+ = 2V, ISINK = 1mA V+ = 5V, ISINK = 1mA V+ = 2V, ISINK = 10mA
15
10 TA = +125C 5
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 V+ - VOH (V)
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 V+ - VOH (V)
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2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
I/O SOURCE CURRENT vs. OUTPUT HIGH VOLTAGE
MAX7311 toc10
MAX7311
I/O HIGH VOLTAGE vs. TEMPERATURE
MAX7311 toc11
50 45 40 35 ISOURCE (mA) 30 25 20 15 10 5 0 0
V+ = 5V TA = -40C
500
400 V+ = 2V, ISOURCE = 10mA V+ - VOH (V)
TA = +25C
300
200
TA = +125C 100 V+ = 5V, ISOURCE = 10mA 0 0.1 0.2 0.3 V+ - VOH (V) 0.4 0.5 0.6 -50 -25 0 25 50 75 100 125 TEMPERATURE (C)
Pin Description
PIN TSSOP/ SSOP/SO 1 2 3 4-11 12 13-20 21 22 23 24 -- THIN QFN 22 23 24 1-8 9 10-17 18 19 20 21 PAD NAME INT AD1 AD2 I/O0-I/O7 GND AD0 SCL SDA V
+
FUNCTION Interrupt Output (Open Drain) Address Input 1 Address Input 2 Input/Output Port 1 Supply Ground Address Input 0 Serial Clock Line Serial Data Line Supply Voltage. Bypass with a 0.047F capacitor to GND. Exposed Pad on Package Underside. Connect to GND.
I/O8-I/O15 Input/Output Port 2
Exposed pad
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2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
AD0 8 BIT INPUT/OUTPUT PORT 1 WRITE PULSE AD2 SMBus CONTROL 8 BIT INPUT/OUTPUT PORT 2 WRITE PULSE V+ READ PULSE POWER-ON RESET I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 INT READ PULSE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
AD1
SCL SDA
INPUT FILTER
N
MAX7311
GND
Figure 1. MAX7311 Block Diagram
SDA
tBUF tSU, DAT tLOW SCL tHD, DAT tSU, STA tHD, STA tSU, STO
tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Detailed Description
The MAX7311 general-purpose input/output (GPIO) peripheral provides up to 16 I/O ports, controlled through an I 2 C-compatible serial interface. The MAX7311 consists of input port registers, output port registers, polarity inversion registers, configuration registers, and a bus-timeout register. Upon power-on, all I/O lines are set as inputs. Three slave ID address select pins, AD0, AD1, and AD2, choose one of 64 slave ID addresses, including the eight addresses supported by the Phillips PCA9555. Table 1 is the register address table. Tables 2-6 show detailed register information.
Serial Interface
Serial Addressing
The MAX7311 operates as a slave that sends and receives data through a 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to and from the MAX7311, and generates the SCL clock that synchronizes the data transfer (Figure 2).
6
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2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
SDA
SCL
S START CONDITION
P STOP CONDITION
Figure 3. START and STOP Conditions
SDA
SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
START CONDITION SCL 1 2 8 9 CLOCK PULSE FOR ACKNOWLEDGMENT
SDA BY TRANSMITTER
S SDA BY RECEIVER
Figure 5. Acknowledge
Each transmission consists of a START condition sent by a master, followed by the MAX7311 7-bit slave address plus R/W bit, a register address byte, 1 or more data bytes, and finally a STOP condition (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 4).
START and STOP Conditions
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the recipient uses as a handshake receipt of each byte of data (Figure 5). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7311, the
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7
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
MAX7311 generates the acknowledge bit since the MAX7311 is the recipient. When the MAX7311 is transmitting to the master, the master generates the acknowledge bit. Slave address pins AD2, AD1, and AD0 choose 1 of 64 slave ID addresses (Table 7).
Data Bus Transaction
The command byte is the first byte to follow the 8-bit device slave address during a write transmission (Table 1, Figure 7). The command byte is used to determine which of the following registers are written or read. Writing to Port Registers Transmit data to the MAX7311 by sending the device slave address and setting the LSB to a logic zero. The command byte is sent after the address and determines which registers receive the data following the command byte (Figure 7).
Slave Address
The MAX7311 has a 7-bit-long slave address (Figure 6). The 8th bit following the 7-bit slave address is the R/W bit. Set this bit low for a write command and high for a read command.
PROGRAMMABLE SDA A6 MSB SDA A5 A4 A3 A2 A1 A0 LSB R/W ACK
Figure 6. Slave Address
Table 1. Command Byte Register
COMMAND BYTE ADDRESS (HEX) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0xFF Input port 1 Input port 2 Output port 1 Output port 2 Port 1 polarity inversion Port 2 polarity inversion Port 1 configuration Port 2 configuration Timeout register Factory reserved. (Do not write to this register.) FUNCTION PROTOCOL Read byte Read byte Read/write byte Read/write byte Read/write byte Read/write byte Read/write byte Read/write byte Read/write byte -- POWER-UP DEFAULT XXXX XXXX XXXX XXXX 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0001 --
SCL
1
2
3
4
5
6
7
8
9 COMMAND BYTE PORT 1 DATA 1 0A 7 6 5 4 3 2 1 0A 7 6 PORT 2 DATA 5 4 3 2 1 0 A
SDA
S
SLAVE ADDRESS R/W
A
0
0
0
0
0
0
START CONDITION WRITE TO PORT
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
DATA OUT PORT 1 tPV READ FROM PORT 2 tPV
Figure 7. Writes to Output Registers Through Write Byte Protocol 8 _______________________________________________________________________________________
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection
Eight of the MAX7311's nine registers are configured to operate as four register pairs: input ports, output ports, polarity inversion ports, and configuration ports. After sending 1 byte of data to one register, the next byte is sent to the other register in the pair. For example, if the first byte of data is sent to output port 2, then the next byte of data is stored in output port 1. An unlimited number of data bytes can be sent in one write transmission. This allows each 8-bit register to be updated independently of the other registers.
ACKNOWLEDGE FROM SLAVE
Reading Port Registers To read the device data, the bus master must first send the MAX7311 address with the R/W bit set to zero, followed by the command byte, which determines which register is accessed. After a restart, the bus master must then send the MAX7311 address with the R/W bit set to 1. Data from the register defined by the command byte is then sent from the MAX7311 to the master (Figures 8, 9).
MAX7311
DATA FROM LOWER OR UPPER BYTE OF REGISTER
DATA FROM LOWER OR UPPER BYTE OF REGISTER
S
SLAVE ADDRESS
0A
COMMAND BYTE
AS
SLAVE ADDRESS
1A
MSB
DATA
LSB
A
MSB
DATA
LSB
NA P
R/W ACKNOWLEDGE FROM SLAVE
R/W
ACKNOWLEDGE FROM SLAVE
MASTER TRANSMITTER BECOMES MASTER RECEIVER AND SLAVE RECEIVER BECOMES SLAVE TRANSMITTER TRANSFER OF DATA CAN BE STOPPED AT ANY TIME BY A STOP CONDITION.
Figure 8. Read from Register
SCL 1 2 3 4 5 6 7 8 9
S
SLAVE ADDRESS R/W
1
A
7
PORT 1 DATA
0
A
7
PORT 2 DATA
0
A
7
PORT 1 DATA
0
A
7
PORT 2 DATA
0
1
P
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER
NONACKNOWLEDGE FROM MASTER
READ FROM PORT 1 DATA INTO PORT 1
READ FROM PORT 2
DATA INTO PORT 2
INT
tIV
tIR
TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.
Figure 9. Read from Input Registers
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9
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
Data is clocked into a register on the falling edge of the acknowledge clock pulse. After reading the first byte, additional bytes may be read and reflect the content in the other register in the pair. For example, if input port 1 is read, the next byte read is input port 2. An unlimited number of data bytes can be read in one read transmission, but the final byte received must not be acknowledged by the bus master. Interrupt (INT) The open-drain interrupt output, INT, activates when one of the port pins changes states and only when the pin is configured as an input. The interrupt deactivates when the input returns to its previous state or the input register is read (Figure 9). A pin configured as an output does not cause an interrupt. Each 8-bit port register is read independently; therefore, an interrupt caused by port 1 is not cleared by a read of port 2's register. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of that I/O does not match the content of the input port register.
Input/Output Port
When an I/O is configured as an input, FETs Q1 and Q2 are off (Figure 10), creating a high-impedance input with a nominal 100k pullup to V+. All inputs are overvoltage protected to 5.5V, independent of supply voltage. When a port is configured as an output, either Q1 or Q2 is on, depending on the state of the output port register. When V+ powers up, an internal power-on reset sets all registers to their respective defaults (Table 1). Input Port Registers The input port registers (Table 2) are read-only ports. They reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the respective configuration register. A read of the input port 1 register latches the current value of I/O0-I/O7. A read of the input port 2 register latches the current value of I/O8-I/O15. Writes to the input port registers are ignored.
OUTPUT PORT REGISTER DATA CONFIGURATION REGISTER SET D Q Q CLR SET D Q Q2 VSS INPUT PORT REGISTER SET D Q Q CLR POWER-ON RESET DATA FROM SHIFT REGISTER WRITE POLARITY PULSE SET D Q POLARITY REGISTER DATA TO INT VDD Q1 100k I/O PIN
DATA FROM SHIFT REGISTER WRITE CONFIGURATION PULSE DATA FROM SHIFT REGISTER WRITE PULSE
Q CLR OUTPUT PORT REGISTER
READ PULSE
INPUT PORT REGISTER DATA
Q CLR POLARITY INVERSION REGISTER
Figure 10. Simplified Schematic of I/Os 10 ______________________________________________________________________________________
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
Table 2. Registers 0x00, 0x01--Input Port Registers
BIT I7 I15 I6 I14 I5 I13 I4 I12 I3 I11 I2 I10 I1 I9 I0 I8
Table 3. Registers 0x02, 0x03--Output Port Registers
BIT Power-up default O7 O15 1 O6 O14 1 O5 O13 1 O4 O12 1 O3 O11 1 O2 O10 1 O1 O9 1 O0 O8 1
Table 4. Registers 0x04, 0x05--Polarity Inversion Registers
BIT Power-up default I/O7 I/O15 0 I/O6 I/O14 0 I/O5 I/O13 0 I/O4 I/O12 0 I/O3 I/O11 0 I/O2 I/O10 0 I/O1 I/O9 0 I/O0 I/O8 0
Table 5. Registers 0x06, 0x07--Configuration Registers
BIT Power-up default I/O7 I/O15 1 I/O6 I/O14 1 I/O5 I/O13 1 I/O4 I/O12 1 I/O3 I/O11 1 I/O2 I/O10 1 I/O1 I/O9 1 I/O0 I/O8 1
Table 6. Register 0x08--Timeout Register
BIT Power-up default 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1
Output Port Registers The output port registers (Table 3) set the outgoing logic levels of the I/Os defined as outputs by the respective configuration register. Reads from the output port registers reflect the value that is in the flip-flop controlling the output selection, not the actual I/O value. Polarity Inversion Registers The polarity inversion registers (Table 4) enable polarity inversion of pins defined as inputs by the respective port configuration registers. Set the bit in the polarity inversion register to invert the corresponding port pin's polarity. Clear the bit in the polarity inversion register to retain the corresponding port pin's original polarity. Configuration Registers The configuration registers (Table 5) configure the directions of the I/O pins. Set the bit in the respective configuration register to enable the corresponding port as an input. Clear the bit in the configuration register to enable the corresponding port as an output.
Bus Timeout Set register 0x08 LSB (bit 0) to enable the bus timeout function (Table 6) or clear it to disable the bus timeout function. Enabling the timeout feature resets the MAX7311 serial bus interface when SCL stops either high or low during a read or write. If either SCL or SDA is low for more than 29ms after the start of a valid serial transfer, the interface resets itself and sets up SDA as an input. The MAX7311 then waits for another START condition.
Standby
The MAX7311 goes into standby when the I2C bus is idle. Standby supply current is typically 2.9A.
Applications Information
Hot Insertion
The I/O ports I/O0-I/O15, interrupt output INT, and serial interface SDA, SCL, AD0-2 remain high impedance with up to 6V asserted on them when the MAX7311 is powered down (V+ = 0V). The MAX7311 can therefore be used in hot-swap applications. Note that each I/O's 100k pullup effectively becomes a 100k pulldown when the MAX7311 is powered down.
Power-Supply Consideration
The MAX7311 operates from a supply voltage of 2V to 5.5V. Bypass the power supply to GND with a 0.047F capacitor as close to the device as possible. For the QFN version, connect the exposed pad to GND.
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2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
Table 7. MAX7311 Address Map
AD2 GND GND GND GND V+ V
+
AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA GND GND V
+
AD0 GND V+ GND V+ GND V
+
A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ADDRESS (HEX) 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x50 0x52 0x54 0x56 0x58 0x5A 0x5C 0x5E
V+ V+ GND GND GND GND V+ V+ V
+
GND V+ SCL SDA SCL SDA SCL SDA SCL SDA GND V+ GND V+ GND V+ GND V
+
V+ GND GND GND GND V+ V+ V+ V
+
V+ GND GND V+ V
+
GND GND GND GND V+ V+ V+ V+
GND GND V
+
SCL SDA SCL SDA SCL SDA SCL SDA
V+ GND GND V+ V+
12
______________________________________________________________________________________
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
Table 7. MAX7311 Address Map (continued)
AD2 SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA GND GND V+ V
+
AD0 GND V
+
A6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ADDRESS (HEX) 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xB0 0xB2 0xB4 0xB6 0xB8 0xBA 0xBC 0xBE 0xC0 0xC2 0xC4 0xC6 0xC8 0xCA 0xCC 0xCE 0xD0 0xD2 0xD4 0xD6 0xD8 0xDA 0xDC 0xDE
GND V+ GND V+ GND V
+
SCL SDA SCL SDA SCL SDA SCL SDA GND V+ GND V
+
GND GND V+ V+ GND GND V+ V
+
GND V+ GND V+ SCL SDA SCL SDA SCL SDA SCL SDA
GND GND V
+
V+
Chip Information
TRANSISTOR COUNT: 12,994 PROCESS: BiCMOS
______________________________________________________________________________________
13
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
INCHES
N
MILLIMETERS MIN 2.35 0.10 0.35 0.23 MAX 2.65 0.30 0.49 0.32
E
H
DIM A A1 B C e E H L
MAX MIN 0.093 0.104 0.004 0.012 0.014 0.019 0.009 0.013 0.050 0.291 0.299 0.394 0.419 0.050 0.016
1.27 7.40 7.60 10.00 10.65 0.40 1.27
1
VARIATIONS: INCHES MILLIMETERS MIN 10.10 11.35 12.60 15.20 17.70 MAX 10.50 11.75 13.00 15.60 18.10 N MS013 16 AA 18 AB 20 AC 24 AD 28 AE
TOP VIEW
D
DIM D D D D D
MIN 0.398 0.447 0.496 0.598 0.697
MAX 0.413 0.463 0.512 0.614 0.713
A e B A1
C 0-8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .300" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0042
B
1 1
14
______________________________________________________________________________________
SOICW.EPS
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SSOP.EPS
MAX7311
2
1
INCHES DIM A A1 B C E H D E e H L MIN 0.068 0.002 0.010 MAX 0.078 0.008 0.015
MILLIMETERS MIN 1.73 0.05 0.25 MAX 1.99 0.21 0.38 D D D D D INCHES MIN 0.239 0.239 0.278 0.317 0.397 MAX 0.249 0.249 0.289 0.328 0.407 MILLIMETERS MIN 6.07 6.07 7.07 8.07 10.07 MAX 6.33 6.33 7.33 8.33 10.33 N 14L 16L 20L 24L 28L
0.20 0.09 0.004 0.008 SEE VARIATIONS 0.205 0.301 0.025 0 0.212 0.311 0.037 8 5.20 7.65 0.63 0 5.38 7.90 0.95 8 0.0256 BSC 0.65 BSC
N
A C e D B A1 L
NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL DOCUMENT CONTROL NO. REV.
21-0056
C
1 1
______________________________________________________________________________________
TSSOP4.40mm.EPS
15
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection MAX7311
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
D
1
2
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
D
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 16 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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